Gray to binary converter circuit
By providing a number of building blocks, an n-bit Gray code to binary conversion circuit can be constructed by selecting and combining the appropriate number of building blocks and then adding ripple logic to complete the computation of the lower order bits. The rearranged data will be written back to the first rows of each bit plane but in the proper pixel order. Image sensors, image processing systems including same, and methods of operating the same. The circuit can either be made with the chips gray to binary converter circuit or with the IC that contains the circuit. Numerous modifications and variations gray to binary converter circuit the scope of the present invention are possible.
Pixel driver that generates, in response to a digital input value, a pixel drive signal having a duty cycle that determines gray to binary converter circuit apparent brightness of the pixel. Low power image sensor adjusting reference voltage automatically and optical pointing device comprising the same. In this case, the logical connection between memory and pixel normalization circuit is greatly simplified.
Memory has stored the pixel values of each pixel before the photodetectors become saturated. Because DPS array outputs pixel data in a gray to binary converter circuit bit arrangement, the pixel data are stored in memory in the form of bit planes. The final normalized data are either outputted on bus in pixel bit arrangement or rewritten to memory via busalso in pixel bit arrangement. In operation, an image is focused on DPS array such that a different portion of the focused image impinges on each of the sensor pixels in the array. According to another aspect of the present invention, pixel normalization circuit includes circuits for performing gray to binary converter circuit pixel data normalization operations as illustrated in FIG.
By providing a number of building blocks, an n-bit Gray code to binary conversion circuit can be constructed by selecting and combining the appropriate number of building blocks and then adding ripple logic to complete the computation of the lower order bits. The process continues until all of the pixel data stored in buffer are processed. In the present embodiment, after CDS subtract circuits operate on the binary pixel data, the CDS normalized pixel data are provided to multiple sampling normalization circuits
After a desired number of sampling, image sensor has captured the light intensity values for all of the pixels in the image. Furthermore, memory includes a memory location for storing the reset values from each of the pixels in DPS array In one embodiment, pixel normalization circuit operates gray to binary converter circuit to rearrange the configuration of the pixel data in memory The resultant memory configuration is the same as the pixel configuration in buffer in FIG.
The pixel normalization circuit is coupled to the data memory for normalizing the pixel data and providing normalized pixel data as output signals. Thus, the first bit of the digital pixel data i. In accordance with one aspect of the present invention, an image sensor includes a sensor array, a data memory and a pixel normalization circuit. The CDS gray to binary converter circuit data are then provided to multiple sampling normalization circuits where the pixel data are normalized using the time index information. When the readings are combined and evaluated via software, the camera can determine the specific color of each segment of the picture.